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cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 1 post office box 655303 ? dallas, texas 75265 ac types feature 1.5-v to 5.5-v operation and balanced noise immunity at 30% of the supply speed of bipolar f, as, and s, with significantly reduced power consumption balanced propagation delays 24-ma output drive current ? fanout to 15 f devices scr-latchup-resistant cmos process and circuit design exceeds 2-kv esd protection per mil-std-883, method 3015 description/ordering information the ?ac74 dual positive-edge-triggered devices are d-type flip-flops. a low level at the preset (pre ) or clear (clr ) inputs sets or resets the outputs, regardless of the levels of the other inputs. when pre and clr are inactive (high), data at the data (d) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. following the hold-time interval, data at the d input can be changed without affecting the levels at the outputs. ordering information t a package ? orderable part number top-side marking pdip ? e tube CD74AC74e CD74AC74e 55 cto125 c soic m tube CD74AC74m ac74m ? 55 c to 125 c soic ? m tape and reel CD74AC74m96 ac74m cdip ? f tube cd54ac74f3a cd54ac74f3a ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. function table (each flip-flop) inputs outputs pre clr clk d q q l h x x h l h lxxl h l lxxh ? h ? h h hh l h h ll h h h l x q 0 q 0 ? this configuration is nonstable; that is, it does not persist when pre or clr returns to its inactive (high) level. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2002, texas instruments incorporated 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1clr 1d 1clk 1pre 1q 1q gnd v cc 2clr 2d 2clk 2pre 2q 2q cd54ac74 ...f p ackage CD74AC74 ...e or m p ackage (top view) on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters.
cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 2 post office box 655303 ? dallas, texas 75265 logic diagram, each flip-flop (positive logic) tg c c tg c c tg c c c tg c c pre clk d clr q q c absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ? 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 1) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): e package 80 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m package 86 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) t a = 25 c ? 55 c to 125 c ? 40 c to 85 c unit min max min max min max v cc supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 v v cc = 1.5 v 1.2 1.2 1.2 v ih high-level input voltage v cc = 3 v 2.1 2.1 2.1 v v cc = 5.5 v 3.85 3.85 3.85 v cc = 1.5 v 0.3 0.3 0.3 v il low-level input voltage v cc = 3 v 0.9 0.9 0.9 v v cc = 5.5 v 1.65 1.65 1.65 v i input voltage 0 v cc 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc 0 v cc v i oh high-level output current v cc = 4.5 v to 5.5 v ? 24 ? 24 ? 24 ma i ol low-level output current v cc = 4.5 v to 5.5 v 24 24 24 ma ? t/ ? v in p ut transition rise or fall rate v cc = 1.5 v to 3 v 50 50 50 ns/v ? t/ ? v input transition rise or fall rate v cc = 3.6 v to 5.5 v 20 20 20 ns/v note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c ? 55 c to 125 c ? 40 c to 85 c unit cc min max min max min max 1.5 v 1.4 1.4 1.4 i oh = ? 50 a 3 v 2.9 2.9 2.9 4.5 v 4.4 4.4 4.4 v oh v i = v ih or v il i oh = ? 4 ma 3 v 2.58 2.4 2.48 v i oh = ? 24 ma 4.5 v 3.94 3.7 3.8 i oh = ? 50 ma ? 5.5 v 3.85 i oh = ? 75 ma ? 5.5 v 3.85 1.5 v 0.1 0.1 0.1 i ol = 50 a 3 v 0.1 0.1 0.1 4.5 v 0.1 0.1 0.1 v ol v i = v ih or v il i ol = 12 ma 3 v 0.36 0.5 0.44 v i ol = 24 ma 4.5 v 0.36 0.5 0.44 i ol = 50 ma ? 5.5 v 1.65 i ol = 75 ma ? 5.5 v 1.65 i i v i = v cc or gnd 5.5 v 0.1 1 1 a i cc v i = v cc or gnd, i o = 0 5.5 v 4 80 40 a c i 10 10 10 pf ? test one output at a time, not exceeding 1-second duration. measurement is made by forcing indicated current and measuring volt age to minimize power dissipation. test verifies a minimum 50- ? transmission-line drive capability at 85 c and 75- ? transmission-line drive capability at 125 c.
cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 4 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range, v cc = 1.5 v (unless otherwise noted) ? 55 c to 125 c ? 40 c to 85 c unit min max min max f clock clock frequency 9 10 mhz t pulse duration pre or clr low 50 44 ns t w pulse duration clk 56 49 ns t setup time data 44 39 ns t su s e t up ti me pre or clr inactive ns t h hold time data after clk 0 0 ns t rec recovery time, before clk clr or pre 34 30 ns timing requirements over recommended operating free-air temperature range, v cc = 3.3 v 0.3 v (unless otherwise noted) (see figure 1) ? 55 c to 125 c ? 40 c to 85 c unit min max min max f clock clock frequency 79 90 mhz t pulse duration pre or clr low 5.6 4.9 ns t w pulse duration clk 6.3 5.5 ns t setup time data 4.9 4.3 ns t su s e t up ti me pre or clr inactive ns t h hold time data after clk 0 0 ns t rec recovery time, before clk clr or pre 4.7 4.1 ns timing requirements over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) ? 55 c to 125 c ? 40 c to 85 c unit min max min max f clock clock frequency 110 125 mhz t pulse duration pre or clr low 4 3.5 ns t w pulse duration clk 4.5 3.9 ns t setup time data 3.5 3.1 ns t su s e t up ti me pre or clr inactive ns t h hold time data after clk 0 0 ns t rec recovery time, before clk clr or pre 2.7 2.4 ns
cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 5 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, v cc = 1.5 v, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) ? 55 c to 125 c ? 40 c to 85 c unit (input) (output) min max min max f max 9 10 mhz t plh clk qq 125 114 ns t phl clk q or q 125 114 ns t plh pre or clr qorq 132 120 ns t phl pre or clr q or q 144 131 ns switching characteristics over recommended operating free-air temperature range, v cc = 3.3 v 0.3 v (unless otherwise noted) (see figure 1) parameter from (input) to (output) ? 55 c to 125 c ? 40 c to 85 c unit (input) (output) min max min max f max 79 90 mhz t plh clk qq 3.5 14 3.6 12.7 ns t phl clk q or q 3.5 14 3.6 12.7 ns t plh pre or clr qorq 3.7 14.7 3.8 13.4 ns t phl pre or clr q or q 4 16.1 4.1 14.6 ns switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) parameter from (input) to (output) ? 55 c to 125 c ? 40 c to 85 c unit (input) (output) min max min max f max 110 125 mhz t plh clk qq 2.5 10 2.6 9.1 ns t phl clk q or q 2.5 10 2.6 9.1 ns t plh pre or clr qorq 2.6 10.5 2.7 9.5 ns t phl pre or clr q or q 2.9 11.5 3 10.4 ns operating characteristics, t a = 25 c parameter typ unit c pd power dissipation capacitance 55 pf
cd54ac74, CD74AC74 dual positive-edge-triggered d-type flip-flops with clear and preset schs231d ? september 1998 ? revised december 2002 6 post office box 655303 ? dallas, texas 75265 parameter measurement information voltage waveforms setup and hold and input rise and fall times t h t su 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v cc 0 v 0 v t r t f reference input data input voltage waveforms propagation delay and output transition times 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% v cc t plh t phl 50% v cc 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 ? , t r = 3 ns, t f = 3 ns. phase relationships between waveforms are arbitrary. d. for clock inputs, f max is measured with the input duty cycle at 50%. e. the outputs are measured one at a time with one input transition per measurement. f. t plh and t phl are the same as t pd . g. t pzl and t pzh are the same as t en . h. t plz and t phz are the same as t dis . from output under test c l = 50 pf (see note a) load circuit s1 2 v cc r1 = 500 ? ? open gnd 0 v t w voltage waveforms pulse duration input 50% v cc 50% v cc v cc t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 output control output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc 20% v cc 50% v cc 0 v voltage waveforms output enable and disable times 50% v cc 50% v cc 80% v cc v cc r2 = 500 ? ? ? when v cc = 1.5 v, r1 = r2 = 1 k ? voltage waveforms recovery time 50% v cc v cc 0 v clr input clk 50% v cc v cc t rec 0 v figure 1. load circuit and voltage waveforms
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples cd54ac74f3a active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 cd54ac74f3a CD74AC74e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 CD74AC74e CD74AC74ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 CD74AC74e CD74AC74m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m CD74AC74m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m CD74AC74m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m CD74AC74m96g4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m CD74AC74me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m CD74AC74mg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 ac74m (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of cd54ac74, CD74AC74 : ? catalog: CD74AC74 ? military: cd54ac74 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant CD74AC74m96 soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) CD74AC74m96 soic d 14 2500 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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